1. Field of the Invention
This invention relates to circuit timing, and more particularly to apparatus and methods to reduce clock and timing skew in integrated circuits.
2. Background of the Invention
As clock speeds continue to increase and cross-die variations becomes harder and harder to control, the ability to align the arrival times of signals that traverse different paths is becoming increasingly challenging. One example is that of minimizing or reducing the skew between two different branches of a clock tree. However, there are many other cases where divergent signals also need to be aligned.
Traditional approaches to align signals are typically design based. For example, clock distribution networks may be designed in the form of H-Trees to ensure that clock branches are symmetric. That is, each level of the clock tree may be designed to have similar gates with similar loading to ensure that propagation delays are as identical as possible through each level of the tree.
Despite these efforts, process variations and other factors may still add significant skew to even perfectly designed H-trees. Such variations may occur in both the gates and wiring network of the circuit. While there are many known sources of variation (e.g., mask/reticle, design, neighborhood effects, wafer location, etc.), there are currently no methods that can accurately predict and correct for these effects. The relatively new field of statistical timing acknowledges a distribution of arrival times for each signal but does nothing to improve the distributions. Although circuits may be designed to account for larger delay distributions, this may significantly degrade the circuits' performance.
In view of the foregoing, what is needed is an apparatus and method to correct timing skew or clock skew in integrated circuits. Ideally, such an apparatus and method would be able to measure timing skew or clock skew with a high degree of precision so that very high-resolution adjustments can be made. Further needed are apparatus and methods to test and programmably correct timing and clock skew in integrated circuits.